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Texas Instruments: 0.09 μm – by mid 2021

Texas Instruments announced plans to introduce a new 0.09 micron process into mass production by mid-2021. The main technological detail reported by the company representatives was that with the new CMOS process technology, the width of the transistor gates will be about 37 nm (0.037 μm).

The new technical process will be used primarily for the production of modern chips used in mobile phones and various wireless devices. Texas Instruments also intends to use this process technology in the UltraSparc processors, manufactured by order of Sun Microsystems.

According to TI spokesman Peter Rickert, the company intends to provide libraries for the development of cost-effective ASIC chips using 0.09 micron process technology (1.8-, 2.5- and 3.3V I / O interfaces, analog / digital -analog and RF macros using optimized analog transistors and capacitors based on high-k dielectrics) by the end of March, completion of work on libraries is scheduled for the third quarter of 2021.

A few words about the process itself. The new 0.09 micron technology combines copper connections with new low-k dielectric materials, which will, for example, bring the density of 6T SRAM memory to 700 Kbps per square millimeter. New process is being developed for use with 300mm and 200mm silicon wafer lines. Nine Layer Copper Joints will be used with Organo-Silicate Glass (OSG) with a low k-value of 2.eight. In addition, the new process technology will use materials developed by TI using plasma nitrided oxide (PNO) to form the transitions of the transistors. TI’s two new 300mm factories in Dallas will be equipped with new technology by mid-2021, but mass production is slated for late 2021. Until then, customers will be testing and modeling.

By the way, as soon as TI confirmed that capital construction costs in 2021 will be reduced to $ 800 million. (indicator of 2021 $ 1.8 billion.), there was information about the company’s plans to increase the volume of orders for chips “on the side”. The funds of TI itself will be used mainly to launch a new 0.09 micron technical process, as well as to re-equip existing lines for the production of analog chips from 150 mm to 200 mm wafers, and lines for the production of standard logic – from 125 mm to 150 mm wafers.

Source: Silicon Strategies

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