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Awaiting the Embedded Processor Forum

The traditional and proven way to improve processor performance until now has been placing cache memory on the processor chip. However, at the Embedded Processor Forum in San Jose, companies at the forefront of new technologies are proposing other ways to improve the performance of their system-on-chip.

For example, MIPS Technologies and ARM chose to use other types of memory outside the processor, instead of locating the cache memory inside the core. The main consideration that guided ARM and MIPS was cost reduction and the ability to give more freedom to ASIC designers. True, there are also critical considerations about the performance of such solutions.

However, not everyone agrees with this proposal. For example, NEC has integrated a 256KB L2 cache and SDRAM controller into its new 64-bit Vr7701 microprocessor core. NEC believes that removing the core from memory can and makes sense for 32-bit low-cost SoCs, but in 64-bit cores it will already lead to performance losses.

But IBM, it seems, will completely go the other way. The 0.13-micron PowerPC 440GX processors use an instruction and data cache of the first level and 256 KB of software-controlled SRAM, providing data exchange with the processor bus at a speed of 5.3 Gb / s.

By the way, at the forum it is expected that Micron Technology will publish details of the SC-1 processor, built using a 32-bit MIPS 4Kc core with 1 MB of embedded DRAM, produced using a 0.18-micron process technology. Micron says the chip will be equipped with an interface for external RAM and flash memory.

Toshiba’s Custom Kernel Announcement Expected. The core will most likely be called a media embedded processor (MeP) and will be intended for use in multimedia devices. Of particular interest in custom cores is STMicroelectronics, which is about to introduce a human face recognition processor based on the Xtensa core licensed from Tensilica.

Well, Tensilica and its competitor, ARC Cores, will talk about their plans to adapt the cores to various tasks. ARC is expected to talk about DSP for VoIP (voice-over-Internet Protocol) and voice-over-DSL, and Tensilica about new instructions for decoding MPEG-4.

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